1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device.
2. Description of Related Art
In vertical semiconductor devices such as IGBTs (insulated-gate bipolar transistors) and FWDs (free-wheeling diodes), it is common for the respective semiconductor areas constituting surface element structures to be formed on the surface of a semiconductor wafer, and for p-type or n-type areas to be formed on the rear surface of the semiconductor wafer. In a Reverse Conducting IGBT (RC-IGBT) that has an IGBT and FWD embedded in the same semiconductor chip, for example, both the p-type and n-type areas are formed on the rear surface of the semiconductor wafer.
A well-known method (hereinafter, the first conventional method) of forming the p-type and n-type areas on the rear surface of the semiconductor wafer includes covering the formation area for one of the p-type and n-type areas with a resist mask, performing ion implantation with this resist mask as the mask in order to inject impurities into the formation area for another semiconductor area, and repeating this twice while changing the conductivity type of the portion covered by the resist mask and the impurities injected during the ion implantation.
Specifically, in the first conventional method, first the rear surface of the semiconductor wafer is coated with resist, and this resist is patterned to form a first resist mask that covers the FWD area and exposes the IGBT area. Next, boron (B) is implanted into the rear surface of the semiconductor wafer with the first resist mask as the mask in order to form a p+ area that serves as a p+ collector region in the IGBT area on the rear surface of the semiconductor wafer. Then, the first resist mask is removed by ashing. Thereafter, the rear surface of the semiconductor wafer is coated with resist again.
Next, the resist is patterned to form a second resist mask that covers the IGBT area and exposes the FWD area. Then, with this second resist mask as the mask, phosphorous (P) is injected into the rear surface of the semiconductor wafer by ion implantation to form an n+ area that serves as an n+ cathode region in the FWD area on the rear surface of the semiconductor wafer. Next, the second resist mask is removed by ashing. Thereafter, the p+ and n+ areas are activated with heat treatment to form the p+ collector region on the IGBT and the n+ cathode region on the FWD.
Another well-known method (hereinafter, the second conventional method) of forming p-type and n-type areas on the rear surface of a semiconductor wafer includes forming one of the p-type and n-type areas on the entire rear surface of the semiconductor wafer by ion implantation, covering the formation area for this semiconductor region with a resist mask, and reversing the conductivity type in the formation area of another semiconductor area exposed to the openings in the resist mask by ion implantation in order to form the other semiconductor area.
FIGS. 8 to 10 are cross-sectional views of a conventional semiconductor device during manufacturing. Specifically, in the second conventional method, a first ion implantation 121 of boron is performed first to form a p+ area 102 on the entire rear surface of an n− semiconductor wafer 101 (FIG. 8). Next, a resist mask 122 that covers an IGBT area 112 and exposes an FWD area 113 is formed on the rear surface of the n− semiconductor wafer 101 (FIG. 9). Then, a second ion implantation 123 is performed to inject phosphorous into the rear surface of the n− semiconductor wafer 101 with the resist mask 122 as the mask, and this converts a portion of the p+ area 102 to an n-type.
The conversion of a portion of the p+ area 102 to the n-type forms an n+ area 103 that serves as an n+ cathode region in the FWD area 113 on the rear surface of the n− semiconductor wafer 101 and leaves the p+ area 102 that serves as a p+ collector region in the IGBT area 112 (FIG. 10). Next, the resist mask 122 is removed by ashing. Thereafter, the p+ area 102 and n+ area 103 are activated with heat treatment to form the p+ collector region of the IGBT and the n+ cathode region of the FWD.
In the first and second conventional methods described above, in general the rear surface of the semiconductor wafer is ground to make the semiconductor wafer thinner, and the above-mentioned methods are used to form the p-type and n-type areas on the thinned rear surface of the semiconductor wafer. Furthermore, the ashing treatment of the resist mask is performed with a conventional ashing device. A device having a structure that raises wafer temperature by using a wafer heating lamp and that is provided in a vacuum preparation chamber connecting a resist ashing treatment chamber to an atmospheric section is proposed as an ashing treatment device used for the ashing treatment of the resist mask, for example (see Patent Document 1 below, for example).
Forming p-type or n-type areas in recesses in the rear surface of the semiconductor wafer are well-known methods, and a method similar to this is proposed as follows. First, a resist is formed on the bottom of the semiconductor layer. At this time, the resist is patterned such that the bottom of the semiconductor layer is exposed in the area where the recesses will be formed. Next, wet etching is performed to form the recesses in the semiconductor layer where the bottom thereof is exposed. Thereafter, the resist is removed. Then, a p-type impurity is injected in the entire bottom of the semiconductor layer to form a p+ area on the entire bottom of the semiconductor layer (see Patent Document 2 (paragraphs 0021 and 0022, FIGS. 3 and 4), for example.)
Another method of forming p-type or n-type areas in recesses in the rear surface of the semiconductor wafer is proposed as follows. Recesses are formed in the bottom of a semiconductor substrate. Wet etching such as isotropic etching using a mixed liquid of hydrofluoric acid and nitric acid or crystalline anisotropic etching using an alkaline solution such as TMAH or KOH is used in the formation of the recesses. Reactive ion etching using a gas containing fluorine or dry etching such as sputter etching can also be used. After the recesses are formed, a collector layer and cathode contact layer are formed on the bottom the semiconductor substrate (see Patent Document 3 (paragraph 0022), for example).